So this is the Sr. Latch which I've talked about in a previous video

And I encourage going back and looking at that video if you're unfamiliar with it, but basically

the latch has two inputs are for reset and then s for set and

when the reset is

goes high then the output Q goes off is reach that reset and

then when the set pin goes high then the

Output Q goes on and then there's also an inverted Q which is always the opposite of q except for one case where if both?

Reset and set inputs are [high] then both of these go off and that's generally considered an invalid

setting this you shouldn't be both setting it and resetting it at the same time and in fact if I

Then release both of these it's kind of arbitrary which one comes on because whichever one of these I'm releasing first kind of wins

But generally yeah, the latch is going to latch in one of these two states

So in this video what I want to do is talk about some modifications to this to this simple, Sr

Latch circuit, so the first thing I look at is that Sr. Latch with and enable, so this is the the basic, Sr

Latch that we just saw

but now we've got on both of the inputs we have these and gates that are connected to an enable signal and

basically what that does is if this enable signal is is high if it's a 1

Then these [an] gates pass through whatever the other input is, so this is a 1 and

Reset is 1 then

It passes through a 1 if is the 1 resets a zero it passes through a 0 if the enable is 0 then

The output is always going to be zero and so [the] latch if enable is 0 the latch always stays latched in its last [state]

and so this just gives us a way to

enable the latch in which case

It's going to pay attention [to] its it's two inputs or

Disable it in which case

It just stays latched regardless of what happens to these inputs so it's just a slight modification of the basic Sr. Latch

We could take this a step further and turn this into a flip-flop and the difference between the Sr. Latch and the Sr

Flip-flop is

And in general the difference between a latch and a flip-flop is that a latch the outputs will change whenever the inputs change

With a flip-flop the outputs are only going to change when there's a clock pulse

and so flip-flops always going to have some sort of clock input and in the

Diagram for it the clock has indicated by this little triangle signal here

And so then whenever the clock pulse comes in or specifically when the clock transitions from low to high in this case

Then the outputs will change and only only at that transition point

Will the outputs change based on whatever the inputs are at that point the rest of the time?

It doesn't matter what's going on with the inputs and so the way [that] works is

we have this clock pulse coming in and it's

You know when it transitions from low to high when those voltage changes here

You're going to get some current flowing through this capacitor as the capacitor charges and so over here. You're going to see the voltage

Go up as soon as this transition takes place

but then once the capacitor charges

That voltage will drop current will stop flowing

Once the capacitor is fully charged and so this clock pulse no matter how long this this clock pulse is is

Going to essentially show up over here [on] the inputs these [an] gates as this

Really quick pulse just at the point where that rising edge happens and so that very quick pulse is used to

essentially enable if we if we think of what we saw before the Sr latch

With the enable it is essentially what's happening over here and so that [Sr]

Latch with enable is is only enabled just [at] that moment where the clock rising edge?

happens and

So that has the effect of it working like an Sr. Flip-flop

[so] when the clock rising edge happens then it looks at the [RnS]

just at that moment where the clock rising edges and if

Reset is is enabled and [set] is not then it resets the output goes to zero and the compliment of the output goes to 1

if the clock rising edge happens and at that moment

The set input is it is active and the reset is not active then the output q

turns on and the complement of Q it goes off and

Then if there's a clock rising edge and both the reset and set inputs are 0 then

It just stays in the last state it stays you know latched like a normally would

[and] in any other case [no] matter if the clock is not

If there's not over izing edge of the clock if the clock is doing anything else

then it doesn't matter what the set and reset is is doing the

Flip-flop stays in its last state now. There's one interesting case here. Which is where?

If you have a clock rising edge and reset and set are both active remember

This is that invalid state, so if reset and set are both active

[you] know we saw before

With just the Sr. Latch if both inputs are active you see

Both Q and the Q complement go off and so you [might] expect [that] right Q and Q complement go off?

but the reality is [that] when we release both of these a latch does settle down in some state and

That's actually going to happen here to one of these two inputs is going to is going to you know be

Slightly ahead of the others and the Sr

Flip-flop is going to settle down into some state so we really aren't actually going to have this

output case where both Q and Q invert

are both 0 so I mean that's invalid right because you would you would you would assume that the

Inverse of Q would be the inverse of q [you] would not expect it to be the same thing and in fact that that's true

And the problem is with this this situation where you have both a set and a reset when you have a clock pulse

It will settle down into the some state, but we don't know what it is. So really

These are both kind of unknown. What will happen, so this is

again kind of an invalid situation or we don't really know what's going [to] happen here because it just

Depends which which of these is is a few nanoseconds faster, you know?

It really it's unpredictable

There is something we can do to make that a little bit more predictable, and that is the Jk Flip-flop

And so the Jk Flip-flop is very similar to the Sr. Flip-flop

Except that it has this feedback coming from the outputs, and so it has these three input and gates over here

And it's looking at the current state of the output Q and and Q inverse in determining

What's going to happen on the input and as far as I know?

You know Jk. Is just kind of an arbitrary set of letters. It doesn't doesn't mean anything

But I guess this is different enough from an Sr. Flip-flop that they gave it a different [name]

But anyway, if we if we walk through what's going to happen here?

You'll see it's [very] similar

so if J and K are both 0 then

It doesn't matter what else is going on the output of these and gates are both 0 and so we have this the same

situation where

You know even if we get a clock pulse?

[we're] going to stay in the last state

but now let's imagine a case where the latch is currently set so q is 1 inverse of Q will be 0

and we want to reset it, so if q is 1

Then this is going to be 1 and

If we want to reset it then we're going to set K to 1 so this input will be 1 because you

[know] the current output is 1 it's currently set

K will be 1 if we want to reset it

and then when we get our clock pulse this and gate will turn on and this will be our reset signal and

That will reset the latch and turn q off and then of [course] the inverse q on and so that's this this scenario here where?

J is 0 K is 1 to reset it and then we get our clock pulse, and so you see Q goes goes low

We reset the latch, but what if the latch was already reset so the latch was already reset then q is already low

and

we set k high and

Basically this this stays off and of course J is also

Low, so this stays off, so we have both zeros and so we stay in the last state

But that's ok right because if we wanted to reset it, we're setting k high to reset it

And it was already reset then it's fine to leave in the last date right where it was already reset

And we want to reset it

Leave it in the last state so that that works fine

[and] same thing in the in the opposite case, so if if it's currently reset

So q is low and inverse q is high then [that] means this is high and so if it's currently reset

And we want to set it with a J

then

both of these inputs will be high and then when we get our clock pulse this input will go high or this output of the

And gate will go high and we'll reset the latch

So you can see in these cases. It works basically the same way as the Sr

Flip-flop, and it's just that we have the inputs are called J and K instead of instead of snr

So where the Jk Flip-flop gets interesting is if both and Kr1?

Because in that case because you've got these these this feedback here J and K [are] both one

but these these these other two signals these feedback are not going to be both one right because

Either one of either q or not q is going to be high at any point in time

you're not going to have both of them high right, so if q is high

Then this lower [en]. Gate will [be] active and the top one will be off, right?

even if J and K are both one if

Inverse of Q is active then the top and gate would be on and the bottom one would be off

So what this does is it means if the latch is currently set then

Effectively, what's going to happen is this lower n. Gate is going to come on in the [latch] [full] reset at the next clock pulse

Whereas if the klatch is currently reset

Then the top and gate would be on and the latch would current would then set at the next clock pulse me assuming J

And k are both or both one and so that gives you this very interesting state where instead of getting some

Invalid or unpredictable output you get this very predictable output. Which is it'll just toggle

So if Q was zero, it'll switch to one if Q was one it'll switch to zero

And as you'll see that's a very interesting property